发明名称 Integrated circuit and method of adjusting capacitance of a node of an integrated circuit
摘要 The present invention relates to an integrated circuit device and method of adjusting the capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block. In a particular embodiment, the method includes selecting a logic state of a digital input (102); applying the digital input to a parasitic capacitance block (130) having an output (110), the output having a first capacitance when the digital input is in first logic state and a second capacitance when the digital input is in a second logic state; and adjusting a capacitance with respect to a second circuit node within the integrated circuit by applying the output to the second circuit node. <IMAGE>
申请公布号 EP1292031(A3) 申请公布日期 2003.10.22
申请号 EP20020255978 申请日期 2002.08.28
申请人 SUN MICROSYSTEMS, INC. 发明人 DROST, ROBERT J.;BOSNYAK, ROBERT J.
分类号 H01L27/08;H03K19/00 主分类号 H01L27/08
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