发明名称 A/D CONVERTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an A/D converting circuit capable of a high-speed operation without affecting a reference voltage in the case of comparison with a low-order comparator due to the fluctuation of the reference voltage with the comparing operation of a high-order comparator. SOLUTION: First switches SW11A-SW13A and second switches SW11B-SW13 B are provided between reference voltage terminals (REF) of high-order comparators COMP11-13 and voltage dividing terminals (N1)-(N3) of a ladder resistor element train, and voltage holding capacitors C11-C13 are connected to the nodes of the first switches SW11A-SW13A and the second switches SW11 B-SW13B. When capturing an input voltage VAIN, the first switches SW11A-SW 13A are turned on to capture high-order reference voltage VN1-VN3 to the voltage holding capacitors C11-C13. When comparison, the first switches SW11A- SW13A are turned off and the second switches SW11B-SW13B are turned on to supply the high-order reference voltages VN1-VN3. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003298421(A) 申请公布日期 2003.10.17
申请号 JP20020093878 申请日期 2002.03.29
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 SUZUKI HISAO
分类号 H03M1/14;(IPC1-7):H03M1/14 主分类号 H03M1/14
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