| 摘要 |
PURPOSE:To handle high-frequency serial data with a low operation clock and to reduce the power consumption of a system by converting an asynchronous signal from serial to parallel at its clock timing, and then performing synchronization. CONSTITUTION:Serial asynchronous data is inputted in its asynchronous state to a serial/parallel converting circuit 14 as it is. This data is converted by the circuit 14 into parallel data Di, which is transferred to a temporary storage circuit 16. Then, the data Di is synchronized with a synchronized timing signal in a data processor 10 and transferred as parallel data Ds to a data bus DB. The signal C1 is synchronized with data read cycles and handled similarly to internal data by selecting the circuit 16 with predetermined address data and also executing a read instruction on the basis of the address data. Namely, high- frequency serial data is handled with a low operation clock, and while the speed of serial asynchronous data to be handled is increased, the power consumption is reduced. |
