| 摘要 |
An adder cell for a ripple-carry adder, suitable for use in an integrated circuit employing CMOS technology, has a gate arrangement for two input variables and a carry input signal, with outputs for sum and carry signals, in accordance with the signals presented to the inputs. The gate arrangement is arranged so that the charging of the capacitance of the carry output takes place from a supply voltage through two transistor gates, not contained in a combination gate, so that one of the transistor gates may be formed as a driving inverter separate from the time-critical carry-propogation path, and designed with significantly lower impedance than the other transistor gates. Alternatively, a single transistor gate is employed for charging the capacitance of the carry output directly form a supply voltage.
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