FIFO memory having reduced scale

摘要

FIFO type memory is provided on a small circuit scale. Reading of data Dout<3:0> from a two-port type RAM (101) is executed with respect to the address specified by a read address (21) in synchronization with the fall of a clock (CLK) provided to a clock end (CLR). Writing of data Din<3:0> on the RAM (101) is executed with respect to the address specified by a write address (22) in synchronization with the rise of a clock (CLK) provided to a clock end (CLW). In an address delayer (103) after a read address (21) taking an address value is outputted, a write address (22) taking the same address value is always outputted with a fixed delay, so that a memory (100) performs the FIFO type data input/output as a whole.