Slack time analysis through latches on a circuit design

摘要

Slack times at an input of a latch in a circuit design are determined by determining a set of required times at the input of the latch, where the set of required times includes a required time entry for each different relationship between a signal comprising a downstream event and a clock signal for the latch. A set of arrival time entries at the input of the latch is also determined, each arrival time entry having a corresponding required time entry.