| 摘要 |
A cache memory includes a plurality of lines of memory and a plurality of cache coherency state registers. Each of the plurality of cache coherency state registers is associated with one of the plurality of lines of memory. Each of the plurality of cache coherency state registers further includes four elements having one of a first value and a second value to form a four bit code for a MESI Protocol. The four bit code provides a first set of codes having a minimum distance of two from every other code, and a second set of codes having a minimum distance of three from every other code. The first set of codes includes a first code representing an Invalid state, a second code representing a Shared state, and a third code representing an Exclusive state. The second set of codes includes a fourth code representing a Modified state.
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