| 摘要 |
PURPOSE: To provide a high speed and high efficient circuit for testing and controlling the array of a RAM. CONSTITUTION: An electronic circuit 10 which operates the control and test of a bank 12 of 8 sets of RAM 141 , 142 , 143 ,..., 14n , is provided with a controller 20 which controls access to those RAMs bank in order to execute a reading and writing operation, and starts the test of those RAMs. This circuit 10 is provided with a data path part 22 which detects a parity error in data written in those RAM and data read from those RAMs, and detects an error which occurs during a test started by the controller 20. Moreover, this is provided with an interface part 24, and a test instruction, state information, and error data are communicated through a four line type boundary scanning bus with the electronic circuit 10 by this interface part 24. |
