Method for fabricating pad oxide layer in semiconductor integrated circuits

摘要

A method for fabricating a pad oxide layer in integrate circuits is described. A zero oxide layer is formed on a silicon wafer, wherein a thickness of the zero oxide layer is slightly greater than the desired thickness of a pad oxide layer that is required in a subsequent process. Photolithography and etching are further conducted to pattern the zero oxide layer and the silicon wafer to form a plurality of alignment marks on the silicon wafer. A cleaning process is further conducted to remove the photoresist layer and a portion of the zero oxide layer to prevent photoresist debris remaining and to control the thickness of the zero oxide layer such that the thickness of the zero oxide layer is same as the desired thickness of the pad oxide layer that is needed in the subsequent process.