发明名称 Method of forming wiring using a dual damascene process
摘要 A method of forming electric wiring using a dual damascene process wherein prevention of damage to a lower conductive pattern and low contact resistance may be achieved. A first insulation layer having a first trench filled with a conductive material is formed on a semiconductor substrate. A first etch stop layer, a second insulation layer and a third insulation layer are sequentially formed thereon. A capping layer is formed on the third insulation layer. A via hole is formed by selectively etching the capping layer, third insulation layer and second insulation layer. Then the capping layer is partially etched and a polymer layer is formed on the exposed first etch stop layer. A second trench is formed and the electric wiring is formed by filling a conductive material in a resulting structure. The polymer layer prevents damage to the conductive pattern by protecting the first etch stop layer.
申请公布号 US6617232(B2) 申请公布日期 2003.09.09
申请号 US20020190478 申请日期 2002.07.09
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM IL-GOO;HWANG JAE-SEUNG
分类号 H01L21/28;H01L21/3205;H01L21/768;(IPC1-7):H01L21/44 主分类号 H01L21/28
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