| 摘要 |
An insulation trench is formed between a drain region formed in a p-type well and a substrate contact region of GG NMOS transistor. The insulation trench extends deeper than the thickness of the p-type well and reaches the p-type substrate of the transistor. This configuration provides a parasitic BJT of the ESD protection transistor with an improves TLP characteristic, and facilitates the operation of the parasitic BJT of the GG MOS transistor accordingly.
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