发明名称 Asynchronous FIFO increment and decrement control for interfaces that operate at differing clock frequencies
摘要 A First-In-First-Out (FIFO) memory device includes a FIFO memory block, a data input interface that writes data into the FIFO memory block in synchronization with a first clock, and a data output interface that reads the data from the FIFO memory block in synchronization with a second clock. The data input interface provides a first indication to the data output interface that the received data has been written into the FIFO memory block. The first indication persists until reset by the data output interface. The data output interface provides a second indication to the data input interface that the received data has been read from the FIFO memory block. The second indication persists until reset by the data input interface.
申请公布号 US6614798(B1) 申请公布日期 2003.09.02
申请号 US19990281520 申请日期 1999.03.30
申请人 INTEGRATED DEVICE TECHNOLOGY, INC. 发明人 BISHOP ROBERT H.;GRUGETT BRUCE C.
分类号 H04L12/56;(IPC1-7):H04L12/54 主分类号 H04L12/56
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