发明名称 |
Integrated circuit memory device having interleaved read and program capabilities and methods of operating same |
摘要 |
A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively. This sub-page programming technique greatly reduces the disturbance and programming time.
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申请公布号 |
US6614715(B2) |
申请公布日期 |
2003.09.02 |
申请号 |
US20020206497 |
申请日期 |
2002.07.25 |
申请人 |
INTEGRATED MEMORY TECHNOLOGIES, INC. |
发明人 |
TSAO CHENG-CHUNG;LIN TIEN-LER |
分类号 |
G11C16/02;G11C7/10;G11C16/06;(IPC1-7):G11C8/00 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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