发明名称 Process for fast cell placement in integrated circuit design
摘要 A process for re-designing IC chips by altering the positions of cells from a first to a second IC chip layout. An x,y grid is established for the first and second IC layouts such that each cell has identifying x,y coordinates in the first layout. Columns are established in the second layout based on the bounds of the second layout in the x-direction. The cells are sorted to the columns in the order of cell x-coordinates to establish new x-coordinates for each cell based on the x-coordinates of the respective column. The cells are sorted in each column to establish y-coordinates for each cell based on the height of the cells in the column and the height of the column.
申请公布号 US2002124233(A1) 申请公布日期 2002.09.05
申请号 US20010756568 申请日期 2001.01.08
申请人 ANDREEV ALEXANDER E.;SCEPANOVIC RANKO;GRINCHUK MIKHAIL I. 发明人 ANDREEV ALEXANDER E.;SCEPANOVIC RANKO;GRINCHUK MIKHAIL I.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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