| 摘要 |
PROBLEM TO BE SOLVED: To provide a hierarchy layout method for semiconductor integrated circuit capable of avoiding a detouring of wiring among function blocks and performing unit reusing for blocks having function for shortening the design time. SOLUTION: A lower hierarchy layout process has a process for selecting the wiring of an upper hierarchy passing on the function blocks from wirings for connecting each function block by referring to wiring information among blocks based on wiring delay time, a process for performing a timing adjustment to satisfy a timing restriction for the wiring of the selected upper hierarchy, a process for generating a region within the lower hierarchy where the wirings pass after the timing adjustment as a wiring inhibition region, a process for arranging a cell and performing wirings in a region within the lower hierarchy except the wiring inhibition region, and a process for releasing the inhibition state of the wiring inhibition region and setting the region where the cell is arranged and the wirings are performed as a layout inhibition region. COPYRIGHT: (C)2003,JPO
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