Combined encryption and decryption circuit and turbo-decoder with such circuit

摘要

Dependent on chosen mode the circuit carries out en- or decryption of a data stream. A data memory (RAM) provides temporary storage, while a first address generator provides a sequence of continuous addresses for the RAM. A second address generator (AG) provides encryption instruction (alpha(i)) representing address sequence for RAM. A first logic module (XOR, MUX) causes second address generator to address RAM for read-out in encryption mode, and for write-in in decryption mode. The action of first address generator is specified. Independent claims are included for turbo-decoder and for method for en- and decryption and turbo-decoding.