DESIGNING AND TESTING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a designing method and a testing method for a semiconductor integrated circuit, enabling high-accuracy testing while suppressing power consumption during the operation of clocks without requiring restrictions on circuits. SOLUTION: In this testing method for a semiconductor integrated circuit, a plurality of scan lines 2 and 3 included in the integrated circuit are put to scanning test by inputting a clock into each of them. The scanning test is performed for at least part of the scan lines by inputting clocks CLK1 and CLK2 with changed duties. This prevents a plurality of circuits on the scan lines from operating simultaneously. COPYRIGHT: (C)2003,JPO