High density semiconductor memory

摘要

Several diagonal bit lines (BLP1-BLPN) are arranged in folded or open bit line configuration that changes horizontal direction along the memory cell array (10) to facilitate access to the memory cells. Several dual word lines (WL1-WLM) are arranged non-orthogonal to the bit lines. The dual word line include a master word line (MWLi) at first layer and second local word lines (LWL1-LWLX) at second layer. The local word lines are being connected to the master word line of common row via several electrical contacts (29). - Memory cell array is comprised by several memory cells (MC) which are arranged in rows and columns. Vertical twist occurs in folded bit lines at each region (33) of the semiconductor memory where change in horizontal direction of bit line configuration occurs. The electrical contacts are arranged in interleaved configuration in alternating rows that have changes in horizontal direction along the memory cell array. The memory cell are 6F2 cells where F represents minimum feature size of memory elements. TECHNOLOGY FOCUS - METALLURGY - The electrical contacts are made up of aluminium material.