Method and apparatus for crossing from an unstable to a stable clock domain in a memory device

摘要

Disclosed is a method and apparatus for converting an unstable receiver enable signal RXEN, which is based on a master clock which undergoes timing adjustments, to a stable receiver enable signal RXEN' which is based on an externally applied clock signal. An externally applied clock signal at a frequency fc is divided by a factor N to produce N uniformly phase spaced clock signals. A clocking edge of a master clock signal which generates the receiver enable signal RXEN is associated with one of the N clocking signals which has a pulse which substantially envelopes the edge of the master clock signal which generates the RXEN signal. A new receiver enable signal RXEN' is generated by the associated new clock signal. The receiver enable signal RXEN is therefore converted from a signal which has adjusted timing to RXEN' which has no timing adjustment.