| 摘要 |
The invention relates to a method for executing instructions in a processor, according to which an instruction to be executed of a programme memory is addressed by a programme control unit by means of a programme counter reading of a programme counter that operates in said unit. The addressed instruction is then read out, decoded and executed by the programme control unit. The aim of the invention is to extend EPIC processor technology by the rapid execution of instruction blocks, thus accelerating the instruction execution, without having to call up subroutines. To achieve this, the programme control unit additionally stores the current programme counter reading and the number of successive instructions when a jump instruction occurs in the form of a block instruction, according to which a specific number of instructions are to be executed successively, thus defining the return address after execution. After the last instruction of the instruction block to be executed, the programme counter resumes the counting operation from the stored programme counter reading. |
