发明名称 |
Semiconductor memory apparatus having cell blocks and column drivers with a column address decoding module and a column drive enable signal generation module arranged to effectively reduce chip size |
摘要 |
A semiconductor memory device including a first memory cell block and a second memory cell block, both cell blocks having memory cells arranged in a matrix, and a common preamplifier/write driver located between and shared by the first memory cell block and the second memory cell block. The first memory cell block and the second memory cell block are aligned in a direction parallel to columns of the memory cells.
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申请公布号 |
US6603701(B2) |
申请公布日期 |
2003.08.05 |
申请号 |
US20020108399 |
申请日期 |
2002.03.29 |
申请人 |
SEIKO EPSON CORPORATION |
发明人 |
MIZUGAKI KOICHI;OTSUKA EITARO |
分类号 |
G11C11/401;G11C5/02;G11C11/403;G11C11/406;G11C11/407;G11C11/409;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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