发明名称 Equalizing circuit and method, and image processing circuit and method
摘要 According to an equalizing circuit and an equalizing method, a memory control unit receives an input of an input image data signal, a first memory stores the input image data signal after delaying it and a CPU designates at least any one of a main scan coordinate and a subscan coordinate to start equalizing of the input image data signal, a main scan size and a subscan size of the equalized block and skew values in a main scan direction and in a subscan direction of the equalized block. Then, a register setting unit holds the setting information which is designated by the CPU and an equalizing control unit performs the equalizing of the input image data signal at a certain timing independently of a skew value of the equalized block on the basis of the setting information held by the register setting unit and outputs the equalized image data signal. Thus, a second memory receives an input of the equalized image data signal from the equalizing control unit and holds it as an output image data signal and an output control unit outputs the output image data of the second memory.
申请公布号 US2003142881(A1) 申请公布日期 2003.07.31
申请号 US20020055402 申请日期 2002.01.25
申请人 TOSHIBA TEC KABUSHIKI KAISHA 发明人 SATOH HIROKI
分类号 G06T5/00;H04N1/409;(IPC1-7):G06K9/40 主分类号 G06T5/00
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