Optimized static sliding-window for ACK sampling

摘要

A control sequencer circuit issues a sequence of commands to logic devices synchronized to a response by a slave device to a command by a master device. In one instance, the control sequencer circuit is statically adjusted to the timing semantics of the acknowledgment signal of the slave device. The control sequencer circuit includes an event detector, a static sliding window, and a sequencer stage. The event detector receives an acknowledgment signal and a requester ID from a slave device and determines if it is the proper recipient. The static sliding window synchronizes the command sequence to the response by the slave device and adjusts for the timing semantics of the acknowledgment signal of the slave device. The control sequencer stage successively outputs active signals at each clock cycle, thereby generating the command sequence.