发明名称 |
Scalable two transistor memory device |
摘要 |
A Scalable Two-Transistor Memory (STTM) cell array having a 4F2 unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.
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申请公布号 |
US2003137063(A1) |
申请公布日期 |
2003.07.24 |
申请号 |
US20030345161 |
申请日期 |
2003.01.16 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
SONG SEUNGHEON;KIM WOOSIK;KANG HOKYU |
分类号 |
H01L27/10;G11C16/04;H01L21/8247;H01L27/115;H01L29/788;(IPC1-7):H01L27/11 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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