| 摘要 |
<p>A single-cycle response pulse width modulator comprising a single error integrating amplifier (U1). The error integrator output is compared to zero to set a flip-flop (FF1). A ramp voltage (VRAMP) is compared to the reference voltage (Vref) to reset the flip-flop (FF1). The ramp voltage (VRAMP) is generated by combination of a resistor (RT) and a current mirror circuit (Q1, Q3, Q4, Q5) coupled to the supply voltage (VP) and charging a capacitor (CT). The flip-flop (FF1) when reset discharges the capacitor (CT). Corrective circuits compensate for delay times in components to maintain substantially constant switching frequency and low distortion in the output voltage. The controller is capable of outputting a predictive triggering signal for associated class-N amplifiers.</p> |
