Electric or electronic circuit arrangement e.g. for microelectronic systems, cells with uniform topological extension or size are used for tuning clock-tree

摘要

Electrical or electronic circuit arrangement having a physical layout (100) with conductor paths (10) and associated cells (30,40) such as flip-flop cells, buffer cells, inverter cells, logic-gate cells or similar. Cells (30,40) assigned for tuning at least one clock-tree of the layout (100) have a mainly unified, topological extension or size. At least one part of the cells (40) is designed as library cells. Independent claims are given for the following: (A) An a method for generating at least one clock-tree. (B) Use of at least one cell for tuning a clock-tree.