发明名称 |
Universal logic module and ASIC using the same |
摘要 |
A universal logic module that may have a reduced off-leak current in universal logic cells ( 100 ) not used as logic circuits has been disclosed. A universal logic module may include universal logic cells ( 100 ) that may be formed with a second wiring for connecting universal logic cells ( 100 ) from a base configuration formed with a first wiring. Unused universal logic cell ( 100 ) may include transistors in basic cells ( A to E ) that are non-connected to a power supply ( VDD ) and/or a ground potential ( VSS ). Furthermore, unused universal logic cell ( 100 ) may include transistors in basic cells ( A to E ) that may provide a capacitor between a power supply ( VDD ) and a ground potential ( VSS ). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.
|
申请公布号 |
EP1326344(A2) |
申请公布日期 |
2003.07.09 |
申请号 |
EP20020028615 |
申请日期 |
2002.12.20 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
YAMAMOTO, KENJI;MIZUNO, MASAHARU;NAKAJIMA, KAZUHIRO |
分类号 |
H01L21/82;H03K19/00;H03K19/173;(IPC1-7):H03K19/173 |
主分类号 |
H01L21/82 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|