| 摘要 |
PURPOSE: A bus architecture for a system chip having a multiprocessor and peripheral blocks is provided to improve the system performance through the extension of a bandwidth and the enhanced entire data processing ratio by separating the data bus between a master and a slave block into a write data bus and a read data bus, and making the master blocks respectively access the slave blocks at the same time. CONSTITUTION: The master blocks(1,2,3) output an address, the write data, and a control signal to the system bus. A bus arbiter(13) processes a request signal outputted from the master blocks(1,2,3). An address decoder(14) decodes the address outputted from the master blocks(1,2,3). The slave blocks(4,5,6) output the data and a response signal after the proper process by receiving the address, the write data, and the control signal outputted from the master blocks(1,2,3). Master multiplexers(7,8,9) output the address, the data, and the control signal of the corresponding master block by receiving a permission signal from the bus arbiter(13). Slave multiplexers(4,5,6) output the data and the response signal of the corresponding slave block by receiving a selection signal from the address decoder(14).
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