| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data processor by constitution from which a PLL circuit is omitted, by reproducing the reproduction of a system clock utilizing PCR to be interposed to a broadcasting signal. <P>SOLUTION: The system clock is generated by a fixed frequency, and decoding processing of encoded data obtained by encoding time series data is carried out according to this system clock. Thus, on the basis of this, STC (present time information) generated on the basis of the system clock and time information (PTS) transmitted from the side of an encoder to designate the output timing of the time series data, the output timing of the time series data to be demodulated is made to synchronize with an output timing designated by PTS. Thus, it is not required to reproduce the system clock synchronizing with the PCR. <P>COPYRIGHT: (C)2003,JPO |
