发明名称 Apparatus for package reduction in stacked chip and board assemblies
摘要 A method and apparatus for assembling semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the interposer substrate and wire bonded to terminals on the opposing substrate surface through an opening in the interposer substrate. Two interposer substrates are placed together with die-carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.
申请公布号 US6583502(B2) 申请公布日期 2003.06.24
申请号 US20010874671 申请日期 2001.06.05
申请人 MICRON TECHNOLOGY, INC. 发明人 LEE TECK KHENG;LEE KIAN CHAI
分类号 H01L25/065;(IPC1-7):H01L29/72 主分类号 H01L25/065
代理机构 代理人
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