发明名称 VERIFY-METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a verify-method of a semiconductor integrated circuit device in which sufficient evaluation of reliability of a non-destruction fuse module after assembling can be performed. <P>SOLUTION: This device is provided with a first transistor Mep0 having a floating gate Fg0 and to which data is written, a second transistor Mer0 having a floating gate Fg0 connected jointly with the floating gate and reading out the data written in the Mep0, and a control gate section 243 coupled to the floating gate and controlling read-out operation of the Mer0. This method is provided with a step by which the first data outputted through the Mer0 when a first potential (normal power source voltage) is applied to the control gate section is compared with the second data outputted through the Mer0 when a second potential (normal power source boosting voltage) is applied to the control gate section, and a step by which verifying of the data is performed based on the compared result, and the first potential is different from the second potential. <P>COPYRIGHT: (C)2003,JPO
申请公布号 JP2003173694(A) 申请公布日期 2003.06.20
申请号 JP20010374609 申请日期 2001.12.07
申请人 ELPIDA MEMORY INC 发明人 DONO CHIAKI
分类号 G01R31/30;G01R31/28;G11C11/401;G11C29/00;G11C29/02;G11C29/04 主分类号 G01R31/30
代理机构 代理人
主权项
地址