| 摘要 |
PROBLEM TO BE SOLVED: To provide a logical circuit design system for facilitating module arrangement, and reducing and facilitating the wiring quantity in arrangement wiring design to be a post-process of a regular design process. SOLUTION: A module dividing part 11 divides the circuit of a design object into a plurality of modules for every function. An address table producing part 12 produces an address table for mapping by respectively making a separating address of a decoder for decoding an input signal supplied to this circuit correspond to the plurality of modules divided by the module dividing part 11. A decoder dividing part 13 divides the decoder and a register for storing a signal converted by this decoder on the basis of the address table made by the address table making part 12. A mapping part 14 relates the respective modules and the decoder for executing logical synthetic processing of the circuit on the basis of a module dividing result by the module dividing part 11 and a decoder dividing result by the decoder dividing part 13. COPYRIGHT: (C)2003,JPO
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