| 摘要 |
A semiconductor memory device secures a margin of data setup time and hold time of a data terminal and includes a delay locked loop, an output replica, an output driver, and an output multiplexer. The delay locked loop compares phases of external and feedback clock signals, and generates internal and delayed internal clock signals. The output replica receives memory cell data, generates the feedback control signal and controls load of a line of the feedback control signal to generate the feedback clock signal, responsive to current control signals for controlling current of the data terminal. The output multiplexer delays the memory cell data by a predetermined time in synchronization with the internal clock signal and responsive to the current control signals. The output driver is driven by the current control signals and the delayed memory cell data, and determines voltage level of the data terminal.
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