发明名称 |
INTERLEAVING ORDER GENERATOR, INTERLEAVER, TURBO ENCODER, AND TURBO DECODER |
摘要 |
In various multi−media services, an enormous memory capacity need not be prepared even when it is necessary to prepare a plenty of types of interleaving patterns. For example, when decoding reception data series of 2 Mbps or above with configuration such as 8−iteration, there is no need of preparing a high−speed memory capacity for temporarily storing the generated interleaving pattern. Furthermore, when the generated pattern needs to be transferred to an interleaving RAM in a turbo decoder actually performing processing, there is no need of preparing such a large amount of transfer data that the interface becomes a bottle neck. It is possible to provide an interleaving order generator, an interleaver, a turbo encoder, and a turbo decoder which can be realized by a minimum parameter transfer never promoting bottle neck on the interface even when a variable rate function is provided and the interleave length changes frequently and solves the problem that the transfer rate in the multi−media service cannot be followed. |
申请公布号 |
WO03044965(A1) |
申请公布日期 |
2003.05.30 |
申请号 |
WO2002JP12082 |
申请日期 |
2002.11.19 |
申请人 |
NEC CORPORATION;MARU, TSUGUO |
发明人 |
MARU, TSUGUO |
分类号 |
H03M13/23;H03M13/27;H03M13/29;H03M13/45;H04B1/707;H04J13/00;H04L1/00 |
主分类号 |
H03M13/23 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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