| 摘要 |
The invention provides for a delay fault testing method and related circuitry for producing a test pulse in response to an input clock signal, and including analysing first and second clock signals having different frequencies and associated with logic circuits having different application speeds, generating a train of two clock pulses for each of the said first and second clock signals, the train of clock pulses being arranged such that the rising edges of the second pulses in each of the said trains are aligned.
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