| 摘要 |
A method for identifying FETs implemented in a predefined logic equation defined by at least one signal name from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity, that includes the steps of selecting an output node from the netlist, preparing the predefined logic equation for searching FETs in the netlist, and identifying FETs from the netlist that are implemented in the prepared predefined logic equation.
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