发明名称 ADDRESSING OF MEMORY MATRIX
摘要 In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among nWORD potentials, while the bit lines are either latched sequentially to potentials selected among nBIT potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto. This timing sequence is provided with a read cycle during which charges flowing between the selected bit line or bit lines connecting thereto are detected and a "refresh/write cycle" during which the polarization of the cells connecting with selected word and bit lines are brought to correspond with a set of predetermined values.
申请公布号 KR20030041955(A) 申请公布日期 2003.05.27
申请号 KR20037000191 申请日期 2003.01.06
申请人 发明人
分类号 G02F1/133;G11C11/22;G09G3/20;G09G3/36;G11C7/06;G11C7/10;G11C8/18 主分类号 G02F1/133
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