SEMICONDUCTOR STORAGE DEVICE

摘要

PURPOSE: To effectively reduce an interference noise generated between adjacent bit lines in one cross (open bit line type) dynamic RAM. CONSTITUTION: Sub-arrays 8, 8 are disposed at the right and left sides of a sense amplifier sequence 7 as a center. Each sub-array has multiple dynamic memory cells MC. A pair of complementary bit lines are constituted of bit lines (BL0, NBL0) to (BLn, NBLn) of the same row at the sub-arrays 8, 8 disposed at the left and right sides of the sequence 7 to become an open bit line type. First wiring patterns SLD formed in parallel with these bit lines and in the same wiring layer are disposed between the bit lines BL0 to BLn, NBL0 to NBLn in the sub-arrays 8, 8. These wiring patterns SLD are all set to a fixed potential such as a power source potential or the like.