发明名称 |
Complementary pass transistor based flip-flop |
摘要 |
A complementary pass transistor based flip-flop (CP flip-flop) having a relatively small layout area and operable at a high speed with reduced power consumption is provided. The CP flip-flop does not need an additional circuit for retaining latched data in a sleep mode. The CP flip-flop receives a clock signal, delays the clock signal for a predetermined time period, and detects the delay time period from the clock signal. The CP flip-flop receives input data for the predetermined delay time and latches the input data until new input data is received. The CP flip-flop is advantageous in that the design of timing for retaining data can be simplified.
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申请公布号 |
US6566927(B2) |
申请公布日期 |
2003.05.20 |
申请号 |
US20010001450 |
申请日期 |
2001.10.22 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
PARK KI-TAE;WON HYO-SIK |
分类号 |
H03K3/012;H03K3/356;(IPC1-7):H03K3/356 |
主分类号 |
H03K3/012 |
代理机构 |
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代理人 |
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地址 |
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