| 摘要 |
<p>PROBLEM TO BE SOLVED: To relax drain disturbance at write of data of a semiconductor integrated circuit device using multi-level storing technology and to reduce a write error largely. SOLUTION: In a flash memory, at write of data, after voltage of approximately 4.1 V is applied to a selection word line S-WL to which a memory cell SW to be written is connected, voltage of approximately 1.2 V being the lower limit voltage of erasure threshold distribution width is applied to a non- selection word line US-WL, after that, voltage of approximately 6.0 V is applied to a local drain LD. A current is not made to flow in each memory cell SDD by voltage of approximately 1.2 V applied to the non-selection word line US-WL, disturbance is relaxed. And a local source LSI is charged through a memory cell S, and word line voltage VWW for write is supplied to the selection word line S-WL. After that, voltage of the non-selection word line US-WL is switched to approximately 4.5 V.</p> |
