| 摘要 |
Circuitry for testing and implementing a distributed tristate bus arrangement. The dirtributed tristate bus arrangement includes a data bus, a first block having at least a first tristate cell including a first enable input for receiving a first enable signal, a first data input for receiving data, a first data output in communication with the data bus, first cascade circuitry having a first cascade circuitry also accepting the first enable input, a cascade output, and first test enabling circuitry for testing the first tristate cell when in a testing mode. A second block having at least a second tristate cell including a second enable input for receiving a second enable signal, a second data input for receiving data, a second data output in communication with the data bus, second cascade circuitry having a second cascade input for accepting a second test signal, the second cascade circuitry also accepting the second enable input, a cascade input operatively connected to the cascade output, and a second test enabling circuitry for testing the second tristate cell when in a testing mode. The circuitry being configured such that in the testing mode, when the first signal is supplied to the first enable input and the test enable signal is operative, the cascade circuitry outputs a cascade out signal to the cascade input via the cascade output, causing the second cascade circuitry to disable the enable input of the second tristate cell, thereby to reduce the possibility of contention of the data bus during scan testing.
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