发明名称 Bit interleave circuit and bit deinterleave circuit
摘要 A bit deinterleave circuit comprises: measurement unit for measuring the reception level of each bit in a received symbol completing a bit interleave process; a command-signal generating unit for outputting a command signal to indicate whether computation in error correction is to be inhibited or permitted for each symbol on the basis of the reception level of the symbol measured by the measurement unit and a threshold value; a first deinterleave unit for deinterleaving the received signal completing a bit interleave process; and second deinterleave unit for rearranging command signals to output the command signals according to a signal output by the first deinterleave unit.
申请公布号 US6564343(B1) 申请公布日期 2003.05.13
申请号 US19990476446 申请日期 1999.12.30
申请人 FUJITSU LIMITED 发明人 YAMASHITA ATSUSHI
分类号 H03M13/27;(IPC1-7):G06F11/00 主分类号 H03M13/27
代理机构 代理人
主权项
地址
您可能感兴趣的专利