摘要 |
Memory devices having redundancy selection circuitry are adapted to introduce test input signals into the redundancy selection path. The memory devices include a redundancy selection circuit having a latch for latching an incoming redundancy match signal. The latch includes a pair of reverse-coupled inverters. The latch is further coupled to receive one or more test input signals. The latch is responsive to one or more control signals to selectively generate the latched match signal from the incoming redundancy match signal or one of the test input signals. Such latch circuits are useful for controlling selection of a redundant element in a memory device during testing without significantly impacting the speed path of the redundancy selection circuitry during normal operation of the memory device.
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