| 摘要 |
<p>When generating a layout for an integrated circuit (IC) based on a netlist design (10), a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced (14). After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout (18). A floor plan is created which imposes spatial constraints based on the trial layout (20) and a timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout (24). The partitions are then separately placed and routed (28).</p> |
