| 摘要 |
PURPOSE: A DRAM type pixel circuit of a liquid crystal display device is provided to drive liquid crystal in a dynamic operation mode in the normal mode while carrying out refresh to a frequency lower than 4Hz without any operation of a driving circuit in a still picture mode, thereby reducing the power consumption. CONSTITUTION: A DRAM type pixel circuit of a liquid crystal display device includes first to fourth NMOS transistors(NM1-NM3), first and second PMOS transistors(PM1,PM2), a storage capacitor(C), and pixel electrodes(PE). The first NMOS transistor has a first current electrode connected to a signal line, a second current electrode connected to a first node(N1), and a control electrode connected to a gate line. The storage capacitor is connected between the first node and a common voltage line(VCOM). The second NMOS transistor has a first current electrode connected to the first node, a second current electrode connected to a pixel electrode, and a control electrode connected to a mode control line(306). The first PMOS transistor has a first current electrode connected to a second node, a second current electrode connected to the pixel electrode, and a control electrode connected to the mode control line. The second PMOS transistor has a second current electrode connected to a driving voltage line(308) and a control electrode connected to the first node. The third NMOS transistor has a first current electrode connected to a pixel voltage line, a second current electrode connected to the second node, and a control electrode connected to the second current electrode of the second PMOS transistor. The fourth NMOS transistor has a first current electrode connected to the common voltage line, a second current electrode connected to the second node, and a control electrode connected to the first node.
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