发明名称 |
POLYPHASE FILTER COMBINING VERTICAL PEAKING AND SCALING IN PIXEL-PROCESSING ARRANGEMENT |
摘要 |
A vertical signal processing circuit including a buffer and a polyphase filter, and adapted to simultaneously process vertical peaking and vertical scaling on pixel data in a first operational mode. In a first operational vertical peaking and scaling mode, the embodiment includes receiving pixel data at a first rate, circulating the data in line buffers and filtering the circulated data through a polyphase filter configured with coefficients derived by convolving peaking filter coefficients with scaling polyphase filter coefficients, and presenting processed pixel data for storage at a second, different pixel rate. Using a control circuit, the pixel-data processing circuit can switch between operational modes by setting different coefficients for the polyphase filter circuit.
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申请公布号 |
WO03036943(A1) |
申请公布日期 |
2003.05.01 |
申请号 |
WO2002IB04223 |
申请日期 |
2002.10.14 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
LIN, CHIEN-HSIN;YEH, BRYAN, L-D. |
分类号 |
H04N5/14;H04N5/208;H04N7/01;(IPC1-7):H04N5/208 |
主分类号 |
H04N5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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