| 摘要 |
A memory subsystem for a computer system includes a memory controller that has a data strobe generator. The memory subsystem further includes a Dynamic Random Access Memory ("DRAM") array coupled to the memory controller and a data path coupled to the data strobe generator and the DRAM array. The DRAM array is separated into two DRAM sets coupled to a common output bus. Access to the DRAM array begins with access to the first DRAM set. After a first Column Address Strobe (CAS) is applied to the first DRAM set, a data strobe is asserted which causes data from the first DRAM set to be latched into the data path. On the next clock cycle after the data strobe is asserted, the data strobe and first CAS are de-asserted. A second CAS is then applied to the second DRAM set on the next clock cycle after the first CAS is de-asserted. In one embodiment, the data path includes a latch that has inputs coupled to the data strobe and an output of the DRAM array via the common output bus. In a further embodiment, the data path includes a flip-flop that has an input coupled to the latch output, and a clock input coupled to the clock.
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