发明名称 Method for potential controlled electroplating of fine patterns on semiconductor wafers
摘要 Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
申请公布号 US6551483(B1) 申请公布日期 2003.04.22
申请号 US20010853959 申请日期 2001.05.10
申请人 NOVELLUS SYSTEMS, INC. 发明人 MAYER STEVEN T.;REID JONATHAN;CONTOLINI ROBERT
分类号 C25D5/18;C25D7/12;H01L21/288;(IPC1-7):C25D21/12;C25D5/00 主分类号 C25D5/18
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