| 摘要 |
A device 212 for generating an output clock signal 213 intended to time a digital processing circuit 204, said generating device receiving a first clock signal 209, characterized in that it comprises an oscillator generating a second clock signal constituting said output clock signal, said oscillator functioning in a forced mode under the control of the rising and falling edges of said first clock signal, said oscillator functioning in a free mode in the absence of rising or falling edges in said first clock signal, the natural frequency of said oscillator being lower than the frequency of said first clock signal. Use: clock signal generator
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