Dual threshold gate array or standard cell power saving library circuits

摘要

A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.